ISRO CSE 2009
Q1.
The microinstructions stored in the control memory of a processor have a width of 26 bits. Each microinstruction is divided into three fields. a micro operation field of 13 bits, a next address field (X), and a MUX select field (Y). There are 8 status bits in the inputs of the MUX. How many bits are there in the X and Y fields, and what is the size of the control memory in number of words?Q2.
Which of the following is/are true of the auto-increment addressing mode? I. It is useful in creating self-relocating code II. If it is included in an Instruction Set Architecture, then an additional ALU is required for effective address calculation III. The amount of increment depends on the size of the data item accessedQ4.
In which addressing mode, the effectives address of the operand is generated by adding a constant value to the content of a register?Q5.
A one dimensional array A has indices 1....75. Each element is a string and takes up three memory words. The array is stored at location 1120 decimal. The starting address of A[49] isQ6.
Suppose the numbers 7,5,1,8,3,6,0,9,4,2 are inserted in that order into an initially empty binary search tree. The binary search tree uses the usual ordering on natural numbers. What is the in-order traversal sequence of the resultant tree?Q7.
The following numbers are inserted into an empty binary search tree in the given order: 10, 1, 3, 5, 15, 12, 16. What is the height of the binary search tree (the height is the maximum distance of a leaf node from the root)?Q9.
The formula \int\limits_{x0}^{xa} y(n) dx \simeq h/2 (y_0 + 2y_1 + \dots +2y_{n-1} + y_n) - h/12 (\triangledown y_n - \triangle y_0) - h/24 (\triangledown ^2 y_n + \triangle ^2 y_0) -19h/720 (\triangledown ^3 y_n - \triangle ^3 y_0) \dots is called